1. Field of the Invention
This invention relates to a semiconductor device and method of manufacturing a semiconductor, especially to a semiconductor having an insulating isolation film between a source and a drain, and method of manufacturing a semiconductor having a switching function using a semiconductor wafer.
2. Related Art
An LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) is proposed as a MOSFET having a high withstand voltage. FIG. 15 is a schematic diagram illustrating a basic structure of a P-channel type LDMOS 1. In FIG. 15, a P-type impurity diffusion layer 3 is formed in an N-type monocrystal silicon substrate 2, and performs as a drift layer of the LDMOS 1. A channel well layer 4 is formed in the impurity diffusion layer 3 by double-diffusing N-type impurities. A source diffusion layer 5 is formed in the channel well layer 4 by diffusing high concentration P-type impurities thereto. Also a potential fixing diffusion layer 6 for fixing a voltage is formed in the channel well layer 4 by diffusing high concentration N-type impurities thereto. A drain-contact layer 7 is formed in the impurity diffusion layer 3 by diffusing high concentration P-type impurities thereto. Between the channel well layer 4 and the drain-contact layer 7 on the impurity diffusion layer 3, a LOCOS oxide film 8 is formed as an insulating isolation film to electrically insulate each other.
On a channel forming region 4a of the channel well layer 4, a gate electrode 9 made of a polysilicon is formed with a gate oxide film 10 interposed therebetween. The gate electrode 9 is formed so that a part of it overlaps onto the LOCOS oxide film 8, that is, a part of it is protruded onto the LOCOS oxide film 8. Furthermore, a drain electrode 11 is ohmic-contacted onto the drain-contact layer 7, and a source electrode 12 is ohmic-contacted onto both of the source diffusion layer 5 and the potential fixing diffusion layer 6.
Here, a power switching element such as the LDMOS 1 is used for a system including the LDMOS 1 and its control circuit, or for a semiconductor device consisting by combining the LDMOS 1 and the control circuit. In this case, in order to evaluate a characteristic of the system or the semiconductor device, a burn-in test, in which a signal for actual operation is applied to the LDMOS 1 while a bias voltage having a rated voltage or more is applied between the source and the drain, is conducted in the final step of the manufacturing procedure, and then characteristic examination is conducted to detect a quality of the element which is deteriorating with time.
Here, in the LDMOS 1 as shown in FIG. 15, both a withstand voltage and a current capability are improved by adequately modifying structural parameters such as an impurity concentration of the impurity diffusion layer 3, an impurity concentration or a junction depth of the channel well layer 4, width size of the LOCOS oxide film 8, a gate overlap length of the gate electrode 9 shown as O/L in FIG. 15 and soon. For example, when the gate overlap length is adequately modified, relations between the gate overlap length and the drain withstand voltage of the LDMOS 1 as shown in FIG. 16A, and between the gate overlap length and the drain current as shown in FIG. 16B are referred. Here, FIGS. 16A, 16B show an example of LOCOS oxide film 8 whose width size is 20 μm. In the case when the characteristics shown in FIGS. 16A, 16B are obtained, the gate overlap length O/L is determined to, for example, around 7 μm.
However, when a burn-in test is conducted on a semiconductor device, which is integrally formed by combining such a LDMOS 1 in which the gate overlap length is adequately modified and a circuit element for controlling the LDMOS 1, it is found that a current capability decrease after conduct of the burn-in test.
To investigate such a phenomenon that the current capability decrease, a bias voltage the same as that in the burn-in test, for example, a bias voltage in which the LDMOS 1 maintains OFF condition even if a temperature of LDMOS 1 rises to substantially 125° C., is applied to the LDMOS 1. In this situation, changes of a relation between a drain voltage and a drain current, and changes of a threshold voltage are measured before and after the application of the bias voltage.
As shown in FIGS. 17A, 17B, it has been found that the threshold voltage values reflect no change between the values measured before and after the application of the bias voltage, whereas the drain current decreases. These results indicate the main factor resulting in the decreased drain current is not decreased threshold voltage, but rather other unknown factors.